1. Field of the Invention
The present invention relates to a method of manufacturing a multilayer circuit substrate, and more particularly to a method of manufacturing a multilayer circuit substrate having a structure that multilevel interconnections are connected with each other through vias.
2. Description of the Prior Art
As an electronic computer becomes higher in operation speed and a semiconductor device becomes larger in capacity and becomes more highly integrated, a method of packaging of a semiconductor device on a substrate has also been changed to a large extent.
In a thin film multilayer circuit substrate, high density packaging, fine interconnection, multilayer formation or the like have become the mainstream, and a plurality of interconnections (conductors) have become to be formed in a small space. Further, in order to achieve high-speed propagation of a signal, it has become indispensable to reduce parasitic capacity by using an insulating film of low dielectric constant.
A thin film multilayer circuit substrate is obtainable by repeating such a process that an interconnection is formed on the insulating film, an insulating film is formed further thereon, and an interconnection is formed on the insulating film. In this case, a conductive via is formed in an interlayer insulating film in order to connect an upper interconnection and a lower interconnection with each other electrically.
A general process of forming vias is as described hereunder. First, photosensitive resin is used as an interlayer insulating film, this photosensitive resin is applied onto a substrate, and then via holes are formed in the photosensitive resin through exposure and development, and the patterned photosensitive resin layer is cured by heating to a predetermined temperature to form an insulating layer. Then, conductive layers are formed on the cured photosensitive resin (or insulating layer) and in the via holes by sputtering, plating or the like. The conductive layers in the via holes become vias, and the conductive layers on the cured insulating layer of the photosensitive resin are formed into patterns so as to become interconnections.
A circuit substrate is formed into a multilayer by repeating such a process as formation of the interlayer insulating films and formation of via holes, vias and interconnections.
In the process of forming via holes in the photosensitive resin that becomes an interlayer insulating film after curing, however, such labor as exposure, development, and curing is required. Further, it forms the via configuration into a step shape to form the via by sputtering or plating, thus causing the via to show a thin layer partially. Such formation of the via into a thin film now incurs high resistance of the via and now causes disconnection at the connecting part between the via and the interconnection.
When photolithography is used in order to form an interconnection on the interlayer insulating film, the throughput of forming the thin film multilayer circuit substrate is decreased. Further, according to a process of photolithography, it is impossible to achieve further miniaturization of the via and formation of higher aspect ratio of the via, and to meet the requirements for high density packaging, fine interconnection, formation of a multilayer or the like attendant upon achievement of high speed of an electronic computer. As to a method of forming an interconnection, a method of having conductive ultra-fine particles project on an insulating film from a nozzle while moving the nozzle, thereby to draw interconnections composed of ultra-fine particles is described in Japanese Patent Provisional Publication No. HEI5-136128 for instance. According to this method, it is impossible to increase the moving speed of the nozzle for the purpose of eliminating configuration defects of the interconnections, and the throughput of forming the interconnections is decreased.
On the other hand, in a conventional thin film multilayer circuit substrate, such a process that an insulating film is formed, via holes are formed in the insulating film, a conductive material is filled in the via holes thereafter so as to form vias and the interconnection is further formed, is repeated a plurality of times sometimes. Since a stress is applied to an interlayer due to heating, patterning or the like performed whenever the insulating film and the conductive film are laminated repeatedly according to this process, these films become to peel off each other more easily.
Thereupon, a method of manufacturing a multilayer circuit substrate by preparing in advance a plurality of insulating films in which vias are formed and interconnections are formed on the upper surface and crimping these plurality of insulating films with heating in a state that they are placed one upon another in order to obtain good connection of multilevel interconnections is described in Japanese Patent Provisional Publication No. HEI5-152755. According to this method, however, since the vias are made to project from the insulating film, a gap becomes liable to be produced in the periphery of the vias and there is a fear that adhesion between insulating films is lowered when the number of vias is large.